Hi all !!!
I am in the middle of getting myself familiar with AT91SAM7X256 port of FreeRTOS. I have found one thing that in my opinion prevents kernel from running (or possibly I don't understand something). When FreeRTOS is configured with
#define configUSE_PREEMPTION1
AIC vector is set to point to vPreemptiveTick function when PIT interrupt event occurs (line 227 in port.c file) The problem is that there is no IRQ interrupt handler which gets AIC interrupt vector by means of reading AT91C_AIC_IVR register.

When FreeRTOS is configured to DO NOT use preemption, PIT interrupt is correctly tied to IRQ (line 136 of portISR.c file), but IRQ handler still is not reading AT91C_AIC_IVR register.

Am I missing something?

Best regards,
Adam

The IVR is read directly by the IRQ interrupt so when an interrupt fires the processor jumps directly to the handler. Look in the startup/boot .s file at where the IRQ interrupt is set up.

Yes, you are right. Thank you for the answer.

But this leads to next question :-)
Acording to ARM7TDMI documentation at the end of ISR handler SPSR is copied to CPSR(and processor mode is changed) when something is written to PC (R15) - for example use of SUB PC,LR, #4 is suggested. If you call a function in ISR, the return address is placed in LR (R14) - BL instruction. If you want to return from this function to "main" ISR, you have to write return address to PC (R15) which will also copy SPSR to CPSR. This copy can cause change processor mode to one before interrupt event, but all of these will happend at the return from function NOT the end of ISR.

How ISR in FreeRTOS deals with such situation when there is a need to call some functions during ISR?

Best regards,
Adam

Yes, you are right. Thank you for the answer.

But this leads to next question :-)
Acording to ARM7TDMI documentation at the end of ISR handler SPSR is copied to CPSR(and processor mode is changed) when something is written to PC (R15) - for example use of SUB PC,LR, #4 is suggested. If you call a function in ISR, the return address is placed in LR (R14) - BL instruction. If you want to return from this function to "main" ISR, you have to write return address to PC (R15) which will also copy SPSR to CPSR. This copy can cause change processor mode to one before interrupt event, but all of these will happend at the return from function NOT the end of ISR.

How ISR in FreeRTOS deals with such situation when there is a need to call some functions during ISR?

Best regards,
Adam

Maybe my question is not clear enough... Let me put it this way:

In order to correctly end ISR, SPSR_irq register should be copied to CPSR. I can not see this happening when I look through disassembly code for ISR. When does it happen?

I found the answer: the problem was in disassembler mnemonic representation, which doesn't show that the S bit in instruction was set.

The final conclusion is when you define the function attribute as interrupt, compiler will take care about setting bit S during return from interrupt. Normal function return always uses instruction with S bit cleared which prevents SPSR->CPSR copy.