Hi,
I have recognized the following certain behavior in the PIC32-demo-project:
The original project works with 80Mhz-SysCLK & 40MHz-PBCLK.
This is realized by the following lines in main.c:
#pragma config FPLLMUL = MUL_20, FPLLIDIV = DIV_2, FPLLODIV = DIV_1, FWDTEN = OFF
#pragma config POSCMOD = HS, FNOSC = PRIPLL, FPBDIV = DIV_2
// SysCLK = 8 / FPLLIDIV * FPLLMUL / FPLLODIV
The compiler itself gets this information by the following lines in FreeRTOSConfig.h:
#define configCPU_CLOCK_HZ( ( unsigned portLONG ) 80000000UL )
#define configPERIPHERAL_CLOCK_HZ( ( unsigned portLONG ) 40000000UL )

I lowered the CPU-Clock by setting FPLLODIV = DIV_2 // DIV4, DIV8, ...
(and customizing FreeRTOSConfig.h)
The PB-Clock is in each case half of the CPU-Clock.

The demo works with 80/40MHz (original settings). It works with 40/20MHz too.
But with 20/10MHz and 10/5MHz failures are reported via LCD-display:
"Error: Gen Q" , "Error: Blck time" ...

Is there anything known?

ralf

The demos do all sorts of the self checks - some more detailed than others. Some will check that an event occurred within the expected time. If you slow the clock right down then the resolution of time measurement will decrease and some tasks will start to think they have missed deadlines. It is not something to worry about, you have just changed the execution environment from that the tasks were expected to find the selves operating under.

Regards.

Thanks for Your answer.
I checked low clock rate under the aspect of minimal power consumption...
But I have another certain behavior... I'll start a new thread

ralf